Floating body FETs, for instance silicon-on-insulator (SOI) MOFETS, exhibit different characteristics than bulk silicon devices. Among these differences are notable advantages, including reduced parasitic source/drain capacitance and enhanced performance at higher switching frequencies. Electrical isolation of the transistor body is not without its drawbacks, however. For example, floating body FETs can exhibit hysteresis, in which a particular FET's prior operational state can result in a shift in its threshold voltage. Because these threshold voltage variations are dynamically produced, they can result in performance instabilities, which may prove particularly problematic, or even harmful, to inverters for example. One of the most important operational parameters influencing hysteresis in a floating body FET is its gate-to-body current. As a result, accurate determination of the gate-to-body current is critical when designing circuits utilizing floating body FETs.
Because a floating body device lacks a body terminal to be accessed for direct measurement, a conventional approach to obtaining an estimate of the gate-to-body current in a floating body FET includes measuring an analogous gate-to-body current in a body-tied FET structure. Various layout configurations have been developed in attempts to improve the accuracy of the estimated gate-to-body current produced by this approach. Nevertheless, data obtained from conventional methods using body-tied devices consistently produce approximations of floating body gate-to-body currents that exaggerate their values, in some instances by substantial factors.